Computer architecture appendix B solutions ASAP?

i need solutions of problem B.1 and B.2 of book computer architecture by john hennessy and patterson 5th edition the B.1 question is L1 cache ,the latencies (in CPU cycles) of different kinds of access are follows: cache hit , 1 cycle ;cache miss,105 cycle; main memory access with cache disable ,100... show more i need solutions of problem B.1 and B.2 of
book computer architecture by john hennessy and patterson 5th edition
the B.1 question is
L1 cache ,the latencies (in CPU cycles) of different kinds of access are follows:
cache hit , 1 cycle ;cache miss,105 cycle; main memory access with cache disable ,100 cycles

a.) when you run a program with an overall miss rate of 5% what will the avg. memory access ?

b.) you use an array of size 256MB (fits in main memory) .Access to random elements of array are cont. made if your data cache is 64KB what will be avg. memory access time be..??

c.) if u compare result of part (b) with main memory access time when cache is disabled ,what do you conclude about role of principle of locality in justifying the use of cache memory..???

d.) you observed that a cache hit produces a gain of 99 cycles,but it produces a loss of 5 cycle in case of miss , we can express this two quantities as G (gain)and L (loss), identify highest miss rate after which cache use would be disadvantageous.

Question B.2 is
we assume we have 512-byte cache with 64-byte blocks . we will also assume that the main memory is 2KB large ,we can regard the memory as an array of 64-byte blocks :M0, M1,M3....M31.and fig B.30 sketches the mem blocks that can reside in different cache blocks if cache is fully associative
a.) show the contents of table if cache is organised as a direct maped cache

please refer book for figure b.30
b.)repeat part (a) with cache organised as 4 way set associative
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