關於Layout Guide的專業翻譯(20點)~

Layout sequence:A→B→C→D→….

A.Lan:

1. Main Asic to PHY(BCM5241A0KMLG) should be less than 12 inches

2. PHY(BCM5241A0KMLG) to RJ45 should be less than 1 inches

3. All data and control signals are minimum of 7 mils wide & space 12 mils.

4. TD+/TD-、RD+/RD- is require to be parallel to each other with the same trace length。

5. PHY TD+/TD- pull-up 49.9 ohm resistors should be close transformer TD+/TD、

6. RD+/RD- pull-down 49.9 ohm resistors should be close transformer RD+/RD

B. USB:

ROUTE USB+/USB- AS A DIFFERENTIAL PAIR ON EXTERNAL LAYER.

FOR 90 OHMS ±10% DIFFERENTIAL IMPEDANCE:

Traces length for all USB signals should be a maximum 12inches

Signal pairs TRACE WIDTH = 8 mils

Signal pairs PAIR SPACING = 10 mils

USB20DMNS –USB20DPLS≦ ±150 mils

USB20DMNS & USB20DPLS space to CLK trace 50 mils(minimum)

CLEARANCE TO OTHER TRACES: 25mil minimum.

EMI cap and resistor must close ASIC in 1 inch

C. DDR2:

1、DQ[0:7] [8:15] , DDR_ADDR0[0:13] length =2 inch(max)

DDR_CLK - DDR_CLKn length = ±1.2 inch(max) ,

Control signals(DDR_CS、DDR_RAS、DDR_CAS、DDR_WE、)=2 inch(max)

2、Differential CLK pairs(DDR_CLK_、DDR_DQS)= +- 0.025 inch(D+ - D-)

3、CLK Trace(DDR_CLK)=5/5 mils, 5mil from differential CLK,

> 20mils between other signals or Vias

4、Control signals:5/10 mils, space others groups 20 mils minimum,

5、: 5/5 mils, space others groups 20 mils minimum,

6、DDR_ADDR0[0:13] : 5/5 mils, space others groups 20 mils minimum,

7、DDR2_VREF trace wide [10mils] and as short as possible

8、DDR_LDQM & DDR_LDQS: 5/9 mils, space others groups 20 mils minimum,

9. U13 &U14 need close to DD2 U6 & U7

D. MOTOR:

(SPACE =30 mile)

Paper_Motor_A=30 mil

Paper_Motor _B=30 mil

Carriage_Motor_A=30 mil

Carriage_Motor_A =30 mil

E: Crystal CLOCK:

Main Asic XIN=15/15 mils

Main Asic XOUT=15/15 mils

Other Crystal CLK In &Out=10 mils

F: FlashRom

SPIDI & SPIDO : 6/10 mils

小弟的電子領域由於剛涉入未深

很多專有名詞上的定義不解~應該說不知道中文常說的意思是什麼

只能大略之ㄧ二!

希望有同樣研發領域的大大們能給予詳解!

(20點)奉上

Update:

噗噗~~!!! 厲害!! 想必一定是EE界老手了~~~ 有沒有及時通可加?

1 Answer

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  • 1 decade ago
    Favorite Answer

    可以請問你在那一家公司部們嗎?因為想換工作才問的,呵呵呵~,不要誤會。

    2010-07-11 19:47:30 補充:

    A. Lan:網路晶片

    1. Main Asic to PHY(BCM 5241A 0KMLG) should be less than 12 inches.

    主晶片到PHY(BCM 5241A 0KMLG)線長須少於12寸,意思是說MAC 到PHY 的接線長度要少於12” 也就是MII介面長度。

    2. PHYBCM 5241A 0KMLG)to RJ45 should be less than 1 inches.

    PHYBCM 5241A 0KMLG)到RJ45線長須少於1寸,目前RJ45已經包含Magnetics當然也有分離的。

    圖片參考:http://imgcld.yimg.com/8/n/AC00916429/o/1610071103...

    http://www.broadcom.com/collateral/pb/5241-PB01-R....

    3. All data and control signals are minimum of 7 mils wide & space 12 mils.

    全部資料跟控制信號線寬W/線距S為,W/S=7/12

    1” =1000 mils

    4. TD+/TD-、RD+/RD- is require to be parallel to each other with the same trace length。

    每一條差動對,不管TX對還是RX對,P跟N要平行繞線和等長也就是Matching通常要求設為5mils(Giga LAN)

    5. PHY TD+/TD- pull-up 49.9 ohm resistors should be close transformer TD+/TD、

    TD+/TD-的PN兩條線將分別各pull-high一個49.9Ω電阻到電源,並且電阻要靠近Magnetics端(通常在RJ45內)

    transformer=Magnetics module

    6. RD+/RD- pull-down 49.9 ohm resistors should be close transformer RD+/RD

    RD+/RD-的PN兩條線將分別各pull-down一個49.9Ω電阻到地,並且電阻要靠近Magnetics端

    這裡TD+/TD-、RD+/RD- 是指MDI bus(Media Dependent Interface)

    B. USB:

    ROUTE USB+/USB- AS A DIFFERENTIAL PAIR ON EXTERNAL LAYER.

    FOR 90 OHMS ±10% DIFFERENTIAL IMPEDANCE:

    將USB差動對繞在PCB外層(TOP/Bottom)有90Ω的阻抗控制

    Traces length for all USB signals should be a maximum 12inches

    所有的USB信號最大線長為12”

    Signal pairs TRACE WIDTH = 8 mils(線寬)

    Signal pairs PAIR SPACING = 10 mils(線距)

    也就是以W/G/W= 8/10/8 繞線方式,差動對彼此的距離我通常叫gap以G代表,其它以S表space。

    USB20DMNS –USB20DPLS≦ ±150 mils(Matching=150)

    USB 差動對 PN長度彼此誤差不能大於150mils

    USB20DMNS & USB20DPLS space to CLK trace 50 mils(minimum)

    CLEARANCE TO OTHER TRACES: 25m il minimum.

    如果USB差動對繞線附近有clock信號線須保持50mils距離,其它只要保持25mils

    EMI cap and resistor must close ASIC in 1 inch

    Decoupling 電容跟一些strip pin電阻須靠近晶片1寸內。

    ****到此已經超過2000字了******

    2010-07-11 19:56:11 補充:

    C. DDR2:

    1、DQ[0:7] [8:15] , DDR_ADDR0[0:13] length =2 inch(max)

    DDR2的資料線跟位址線最大長度2寸

    DDR_CLKp- DDR_CLKn length = ±1.2 inch(max)

    直接翻譯為DDR_CLK的PN相減長度要在1.2”內,不過很怪你是不是打錯了。

    Control signals(DDR_CS、DDR_RAS、DDR_CAS、DDR_WE、)=2 inch(max)

    以上信號Intel layout Guide通常稱為Command Group而不是Control Group,最大長度2寸。

    2010-07-11 19:57:27 補充:

    ****續~~只能用意見了***

    2010-07-11 19:58:21 補充:

    2、Differential CLK pairs(DDR_CLK_、DDR_DQS)= +- 0.025 inch(D+ - D-)

    DDR_CLK或DDR_DQS差動對的PN相減長度(Matching)要在25mils內,也就是說PN差動對(D+ - D-)彼此誤差不能大於25mils,一般還是會設成5mils,信號品質會比較好。

    2010-07-11 19:58:32 補充:

    3、CLK Trace(DDR_CLK)=5/5 mils, 5mil from differential CLK,> 20mils between other signals or Vias(這裡應該是DDR2 clock 的差動對才對,但這裡的表示有點奇怪,所以我還是以原本的意思說明)一般單線Clock應該是指低頻clock信號(33M/48M),繞線方式為 W/S=5/5 or 5/20

    距clock差動對使用5/5;距Via或其它信號用5/20。

    2010-07-11 19:58:42 補充:

    4、Control signals:5/10 mils, space others groups 20 mils minimum,

    控制信號群組DDR_CS、DDR_RAS、DDR_CAS、DDR_WE、)使用繞線方式為 W/S=5/10 or 5/20

    距群組內信號使用5/5;距非群組內信號用5/20。

    2010-07-11 19:58:56 補充:

    5、: 5/5 mils, space others groups 20 mils minimum,

    距群組內信號使用5/5;距非群組內信號用5/20。但不知道應用在那一組信號

    6、DDR_ADDR0[0:13] : 5/5 mils, space others groups 20 mils minimum,

    DDR_ADDR的位址線群組,距群組內信號使用5/5;距非群組內信號用5/20。

    2010-07-11 19:59:13 補充:

    7、DDR2_VREF trace wide [10mils] and as short as possible

    DDR2信號參考準位線寬=10mils且盡可能的短

    8、DDR_LDQM & DDR_LDQS: 5/9 mils, space others groups 20 mils minimum,

    距群組內信號使用5/9;距非群組內信號用5/20

    9. U13 &U14 need close to DD2 U6 & U7

    U13和U14須要靠近DD2的U6和U7

    2010-07-11 19:59:38 補充:

    D. MOTOR:(馬達)

    (SPACE =30 mile)(線距)

    Paper_Motor_A=30 mil(線寬)

    Paper_Motor _B=30 mil(線寬)

    Carriage_Motor_A=30 mil(線寬)

    Carriage_Motor_A =30 mil(線寬)

    2010-07-11 19:59:51 補充:

    E: Crystal CLOCK:(水晶時鐘信號)

    Main Asic XIN=15/15 mils(主晶片clock input, 使用W/S=15/15)

    Main Asic XOUT=15/15 mils(主晶片clock output, W/S=15/15)

    Other Crystal CLK In &Out=10 mils(其它水晶時鐘信號, W/S=15/10)

    2010-07-12 00:07:21 補充:

    F: FlashRom(快閃記憶體)

    SPIDI & SPIDO : 6/10 mils}(使用W/S=6/10)

    我想應該不是音效卡的「S/PDIF」接頭有關,因為跟FlashRoom沒什麼關系,我猜應該是SPI介面Nor Flash的 data input/output。

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