VHDL 同步數位電路

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將下圖以VHDL描述

http://www.wretch.cc/album/show.php?i=tom80106c&b=...

如果告訴我答案的給20點

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  • 1 decade ago
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    ------------------------------------------------------

    circuit檔案

    library ieee;

    use ieee.std_logic_1164.all;

    entity circuit is

    port(

    en : in std_logic;

    clr: in std_logic;

    clk: in std_logic;

    q : out std_logic

    );

    end circuit;

    architecture behavior of circuit is

    component T_FF

    port(

    T : in std_logic;

    clr: in std_logic;

    clk: in std_logic;

    q : out std_logic

    );

    end component;

    signal q1,q2,q3,q4:std_logic;

    signal y1,y2,y3:std_logic;

    begin

    y1<=q1 and en;

    y2<=q2 and y1;

    y3<=q3 and y2;

    u1: T_FF port map( T =>en,

    clr =>clr,

    clk =>clk,

    q =>q1 );

    u2: T_FF port map( T =>y1,

    clr =>clr,

    clk =>clk,

    q =>q2 );

    u3: T_FF port map( T =>y2,

    clr =>clr,

    clk =>clk,

    q =>q3 );

    u4: T_FF port map( T =>y3,

    clr =>clr,

    clk =>clk,

    q =>q );

    end behavior;

    ---------------------------------------------------------------

    T_FF檔案

    library ieee;

    use ieee.std_logic_1164.all;

    entity T_FF is

    port(

    T : in std_logic;

    clr: in std_logic;

    clk: in std_logic;

    q : out std_logic

    );

    end T_FF;

    architecture behavior of T_FF is

    signal q_temp:std_logic;

    begin

    q<=q_temp;

    process (clr,clk) begin

    if(clr='0') then

    q_temp<='0';

    elsif (rising_edge(clk)) then

    if(T='0') then

    q_temp<=q_temp;

    else

    q_temp<=not(q_temp);

    end if;

    end if;

    end process;

    end behavior;

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