# VHDL除16之上數計數器程式

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Lv 6

你好，

請試試這個，看看是否合用？

CNT4T 是一個4位元的除16上數計數器，它叫用了TFF這一個我自己寫的 T-型正反器。

-- -----------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity CNT4T is Port (

RST,CLK : in std_logic;

Q : out std_logic_vector(3 downto 0));

end CNT4T;

architecture arch of CNT4T is

component TFF is port (

RST,CLK,T : in std_logic;

Q : out std_logic);

end component TFF;

signal TQ : std_logic_vector(3 downto 0);

signal TI : std_logic_vector(3 downto 0);

begin

TI(0) <= '1';

TI(1) <= TQ(0);

TI(2) <= TQ(1) and TQ(0);

TI(3) <= TQ(2) and TQ(1) and TQ(0);

T0 : TFF port map(RST=>RST, CLK=>CLK, T=>TI(0), Q=>TQ(0));

T1 : TFF port map(RST=>RST, CLK=>CLK, T=>TI(1), Q=>TQ(1));

T2 : TFF port map(RST=>RST, CLK=>CLK, T=>TI(2), Q=>TQ(2));

T3 : TFF port map(RST=>RST, CLK=>CLK, T=>TI(3), Q=>TQ(3));

end arch;

-- -----------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity TFF is port (

RST,CLK,T : in std_logic;

Q : out std_logic);

end entity TFF;

architecture arch of TFF is

signal TQ : std_logic;

begin

p_tff : process(RST,CLK)

begin

if (RST='1') then

TQ <= '0';

elsif (CLK'event and CLK='1') then

if (T='1') then

TQ <= not TQ;

end if;

end if;

end process p_tff;

Q <= TQ ;

end architecture arch;