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Since the pulses generated by the oscillator-II are accumulated as the phase angle, the VSI output frequency is adjustable while varying the output frequency of the oscillator-I. Another advantage of the phase angle counter is that the circulative counting with auto-reset capability is analogous to the vector control in the polar coordinate. The overflow problem while accumulating the clock pulses is therefore can be avoided. The first-two positions of the output digits of phase angle counter herein denotes as high-order bits (HB) and the remainder as the low-order bits (LB), as shown in Fig. 5.

The symmetric property of the HEPWM waveform is advantageous to reduce the memory need for the EPROM. In Fig. 6, it is clear that the LB is in charge of the phase angle in the range of 0 to π/2, only the LB and the modulation index are needed to be scheduled as the address inputs for the EPROM. In order to determine the switching patterns, a logic circuit was proposed to read the stored data circularly. The first step of this control logic is to transform a one-cycle phase angle within the 0 to π/2 interval. The phase angle output (φ90) of the clock control circuit can be expressed by truth table as follow:

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### 1 Answer

- 1 decade agoFavorite Answer
VSI 輸出頻率由於脈衝由振盪器-II 生成累積作為階段角度中，是時不同的振盪器輸出頻率可調-我。 階段角度計數器另一個優點是具有自動重置功能迴圈點票是類似于媒介控制在極地座標。 溢出問題累積時鐘脈衝因此是可以避免。 第一個位置的輸出位數的階段角度計數器此處表示為高序位 (HB) 和其餘作為低順序比 (LB) Fig.5 所示。

HEPWM 波形，對稱屬性是減少記憶體需要為該 EPROM 有利。 Fig.6 中很明顯該 LB 是以該範圍 （0 階段角度，為 π / 2 的主管，需要只 LB 和調製索引為該 EPROM 排定為位址輸入。 為了確定切換模式，邏輯電路被建議 circularly 讀取存儲的資料。 此控制項邏輯，第一步是轉換內 0 π / 2 的間隔的一個週期階段角度。 可以用真相表如按照表示的時鐘控制電路階段角度輸出 (φ90)：

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