關於VHDL程式問題。。

希望有大大能幫我找出錯誤語法在哪裡。。。

拜託><。。麻煩幫我修正一下。。

謝謝。。

entity test2 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

g : out STD_LOGIC);

end test2;

architecture Behavioral of test2 is

begin

if a='0' then

g <= b;

else

g <= a;

end if;

end Behavioral;

------------------

entity test1 is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

g : out STD_LOGIC_VECTOR (2 downto 0));

end test1;

architecture Behavioral of test1 is

begin

process(a,b)

begin

if a='0' then

g <= b;

else

g <= a;

end process;

end Behavioral;

---------------

architecture Behavioral of div2 is

signal count: std_logic_vector(1 downto 0);

begin

div:process(clk)

begin

if clk'event and clk='1' then

count <= count + 1;

end if;

clkm = count(2);

end Behavioral;

上面有3個程式。。

Update:

還有一提。。

architecture Behavioral of div is

begin

process(clk)

signal clk_count : std_logic_vector(n1-1 downto 0):= (others => '0');

if rising_edge(clk) then

clk_count <= clk_count +1;

end if;

clk1 <= clk_count(n1-1);

clk2 <= clk_count(n2-1);

end Behavioral;

1 Answer

Rating
  • ?
    Lv 6
    1 decade ago
    Favorite Answer

    你好,

    這是四個獨立的小程式,最好是四個獨立的檔案,因此依序說明如下,每一個部分,試者讓他通過VHDL的編譯為原則,至於功能是否正確,則必須另外討論。

    --開頭的行是說明,編譯成功後請刪除。

    --第一隻程式:

    --請加入程式庫的宣告

    Library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_arith.all;

    use ieee.std_logic_unsigned.all;

    entity test2 is

    Port (

    a : in STD_LOGIC;

    b : in STD_LOGIC;

    g : out STD_LOGIC);

    end test2;

    architecture Behavioral of test2 is

    begin

    --if 敘述必須在 process 裡頭進行,加入

    -- process(a,b) begin .... end process;

    process(a,b) begin

    if a='0' then

    g <= b;

    else

    g <= a;

    end if;

    end process;

    end Behavioral;

    --

    --第二隻程式:

    --請加入程式庫的宣告

    Library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_arith.all;

    use ieee.std_logic_unsigned.all;

    entity test1 is

    Port (

    a : in STD_LOGIC_VECTOR (3 downto 0);

    b : in STD_LOGIC_VECTOR (3 downto 0);

    --g 的大小應該與a及b相同,擅自修改成(3 downto 0)

    g : out STD_LOGIC_VECTOR (3 downto 0));

    end test1;

    architecture Behavioral of test1 is

    begin

    process(a,b)

    begin

    --為防止不必要的錯誤,請以a="0000"來寫判斷式

    if a="0000" then

    g <= b;

    else

    g <= a;

    end if;

    end process;

    end Behavioral;

    --

    2008-11-15 05:46:23 補充:

    --太長了,.......

    --第三隻程式:

    --請加入程式庫的宣告

    Library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_arith.all;

    use ieee.std_logic_unsigned.all;

    --除非另外有entity的宣告,否則不可省,

    --這是擅自猜測可能的寫法

    entity div2 is

    Port (

    clk : in STD_LOGIC;

    clkm : out STD_LOGIC);

    end div2;

    2008-11-15 05:46:47 補充:

    architecture Behavioral of div2 is

    signal count: std_logic_vector(1 downto 0);

    begin

    div:process(clk)

    begin

    if clk'event and clk='1' then

    count <= count + 1;

    end if;

    end process div;

    2008-11-15 05:46:55 補充:

    --count這一信號的宣告是 (1 downto 0),所以count(1)才合理;

    --或是修改這一行:signal count: std_logic_vector(2 downto 0);

    clkm <= count(1);

    end Behavioral;

    --

    2008-11-15 05:47:36 補充:

    --第四隻程式:

    --請加入程式庫的宣告

    Library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_arith.all;

    use ieee.std_logic_unsigned.all;

    2008-11-15 05:47:41 補充:

    --除非另外有entity的宣告,否則不可省,

    --因為內部使用到 n1 及 n2 的常數,增加在generic中宣告

    --這是擅自猜測可能的寫法

    entity div is

    generic (

    n1 : integer:=3;

    n2 : integer:=2);

    Port (

    clk : in STD_LOGIC;

    clk1,clk2 : out STD_LOGIC);

    end div;

    2008-11-15 05:48:12 補充:

    architecture Behavioral of div is

    --clk_count 應以 signal宣告為佳,因此自process中一到這裡;

    --在 process 宣告的形式只能是 variable;

    --n1,n2 常數,宣告在generic中

    signal clk_count : std_logic_vector(n1-1 downto 0):=(others=>'0');

    begin

    2008-11-15 05:48:34 補充:

    process(clk)

    begin

    if rising_edge(clk) then

    clk_count <= clk_count +1;

    end if;

    end process;

    --n1,n2 常數,宣告在generic中

    clk1 <= clk_count(n1-1);

    clk2 <= clk_count(n2-1);

    end Behavioral;

    --

    2008-11-15 05:51:17 補充:

    --補充說明:太長了,好不容易分段補充完畢,請由上到下依序接起來看,本人有嚐試編譯過,應該是OK了,祝你一次成功!

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