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IC規格書翻譯

13.1.8 Unused I/O pins

Unused I/O pins should have a defined level and not be left floating. One way to do this is to leave the pin unconnected and configure the

pin as a general purpose I/O input with pull-up resistor. This is also the state of all pins during reset. Alternatively the pin can be configured

as a general purpose I/O output. In both cases the pin should not be connected directly to VDD or GND in order to avoid excessive power consumption.

13.1.9 Low I/O Supply Voltage

In applications where the digital I/O power supply voltage pin DVDD is below 2.6 V, the register bit PICTL.PADSC should be set to 1 in

order to obtain output DC characteristics specified in section 7.16.

13.1.10 I/O registers

The registers for the I/O ports are described in this section. The registers are:

13.2 DMA Controller

The CC2430 includes a direct memory access (DMA) controller, which can be used to relieve the 8051 CPU core of handling data movement operations thus achieving high overall performance with good power

efficiency. The DMA controller can move data from a peripheral unit such as ADC or RF transceiver to memory with minimum CPU intervention.

The DMA controller coordinates all DMA transfers, ensuring that DMA requests are prioritized appropriately relative to each other and CPU memory access. The DMA controller contains a number of programmable DMA channels for memory-memory data movement.

The DMA controller controls data transfers over the entire address range in XDATA memory space. Since most of the SFR registers are mapped into the DMA memory space, these flexible DMA channels can be

used to unburden the CPU in innovative ways, e.g. feed a USART with data from memory or periodically transfer samples between ADC and memory, etc.

1 Answer

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  • Leo
    Lv 7
    1 decade ago
    Favorite Answer

    13.1.8 Unused I/O pins未使用的輸入/輸出端子

    未使用的輸入/輸出端子應該有一個被定義的狀態而不是丟著不管. 有一種處理方式是把這些端子保留在沒有接線的狀態然後把它們用昇值電阻規劃成為一般用途的輸入/輸出端子. 在重新設定的狀態下這也是所有端子的狀態. 另外, 這些端子也可以規劃成一般用途輸入/輸出的輸出端. 在這兩種情況下這些端子都不應該直接與VDD(直流電壓輸入端)或GND(接地端)連接以避免過不必要的電力消耗.

    13.1.9 Low I/O Supply Voltage低輸入/輸出電源電壓

    當在數位輸入/輸出電源電壓端子的DVDD在2.6 V以下之應用, PICTL.PADSC的計數器端應該設定到1來獲得第7.16節規範的輸出直流電壓特性.

    13.1.10 I/O registers 輸入/輸出計數器

    The registers for the I/O ports are described in this section. The registers are:

    計數器的輸入/輸出連接滬在這一節描述. 計數器是:

    13.2 DMA Controller直接記憶體存取控制器

    CC2430包括一個直接記憶體存取(DMA)控制器, 可以被來釋放8051CPU中央處理器處理數據移轉作業的核心因而達成高整體效能而且具有良好的耗電效率. DMA控制器可以用最低的CPU干預從ADC或RF接受器等等的週邊元件轉換數據到記憶體.

    DMA控制器協調所有DMA的轉移, 保證DMA的需求依相互的運作以及CPU記憶體存取適當地給予優先定義. DMA控制器包含一定數量的可編程DMA頻道供記憶體對記憶體數據的轉移.

    DMA控制器控制整個XDATA記憶體空間所有位址範圍的數據轉移. 因為大多數的SFR計數器被置入DMA記憶體中, 這些可變的DMA頻道可以被用來以創新的方式減輕CPU的負擔, 意即, 由記憶體把數據送進USAR或週期性地在ADC和記憶體等等之間轉移樣品數據.

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