? asked in 電腦與網際網路程式設計 · 1 decade ago

我最後的FourBCDadd_sub怎麼改(Verilog)

我已經有4bcd加法器的模組

七段顯示器模組

九補數模組

差最後的線盒在ㄧ起

module FourBCDadd_sub (a, b, cin, y, cy);

input [3:0]a;

input [3:0]b;

input cin;

output [6:0] y;

output cy;

wire [3:0]f,s;

assign nine_comp z1 (ctrl,b,f);

BCDfull_4adder z2 (a,f,s,ctrl,cy);

seven_seg z3 (s,y);

endmodule

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1 Answer

Rating
  • Bing
    Lv 4
    1 decade ago
    Favorite Answer

    assign nine_comp z1 (ctrl,b,f); ----> 這一行不用加assign

    Source(s): 自己
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