Anonymous
Anonymous asked in 電腦與網際網路程式設計 · 1 decade ago

VHDL程式設計問題~~

剛好要做到類似像~~~

輸入一條 12bit 的訊號 , 然後輸出會分成各 4bit 的三輸出 要如何寫呢@@?? (使用vhdl)

先謝謝了~~~ ^^

2 Answers

Rating
  • dtsien
    Lv 6
    1 decade ago
    Favorite Answer

    library ieee;

    use ieee.std_logic_1164.all;

    entity Spliter is

    port(IN: in std_logic_vector(11 downto 0);

    O2: in std_logic_vector(3 downto 0);

    O1: in std_logic_vector(3 downto 0);

    O0: in std_logic_vector(3 downto 0)

    );

    end Spliter;

    architecture behv of Spliter is

    begin

    process(IN)

    begin

    O2 <= IN(11 downto 8);

    O1 <= IN(7 downto 4);

    O0 <= IN(3 downto 0);

    end process;

    end behv;

  • ?
    Lv 6
    1 decade ago

    dtsien大大的方法OK!

    但是多個信號重新組合成一個信號、一個信號分離成多段、指定別名、及重新指定信號的名稱等,其實可以不必 PROCESS,所以原ARCHITECTURE可以簡單寫成:

    architecture behv of Spliter is

    begin

    O2 <= IN(11 downto 8);

    O1 <= IN(7 downto 4);

    O0 <= IN(3 downto 0);

    end behv;

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