急~verilog期末報告

要設計一個東西~可以給我建議嗎~或幫我寫一個程式出來~謝謝!

例如~寫一個紅綠燈~或是比較器~或是序向邏輯的電路~

有附圖的話最好~拜託各位高手幫幫忙><

Update:

樓下那位能幫我補上TESTBENCH嗎

2 Answers

Rating
  • 1 decade ago
    Favorite Answer

    `timescale 1ms/1ns

    module red_green_light (reset, clk_1sec, Red, Green, Yellow);

    inputreset;// 1:Reset system

    inputclk_1sec;// clock frequency = 1 sec

    outputRed, Green, Yellow;

    parameter Idle = 2'h0,

    Red_st = 2'h1,

    Green_st = 2'h2,

    Yel_st = 2'h3;

    parameter Red_time = 8'h64,// Red time = 100 sec

    Green_time = 8'h50,// Green time = 80 sec

    Yellow_time = 8'h06;// Yellow time = 6 sec

    reg [1:0] state, nx_state;

    reg [7:0] time_cnt;

    reg Red, Green, Yellow;

    always @ (state or time_cnt)

    begin

    case (state)

    Idle : nx_state = Red_st;

    Red_st: begin

    if (time_cnt == Red_time)

    nx_state = Green_st;

    else

    nx_state = state;

    end

    Green_st : begin

    if (time_cnt == Green_time)

    nx_state = Yel_st;

    else

    nx_state = state;

    end

    Yel_st: begin

    if (time_cnt == Yellow_time)

    nx_state = Red_st;

    else

    nx_state = state;

    end

    default : nx_state = state;

    endcase

    end

    always @ (posedge clk_1sec)

    begin

    if (reset)

    state <= #1 Idle;

    else

    state <= #1 nx_state;

    end

    always @ (posedge clk_1sec)

    begin

    if (state == Idle)

    time_cnt <= #1 8'h00;

    else if (((state == Red_st) & (time_cnt == Red_time)) |

    ((state == Green_st) & (time_cnt == Green_time)) |

    ((state == Yel_st) & (time_cnt == Yellow_time)))

    time_cnt <= #1 8'h00;

    else

    time_cnt <= #1 time_cnt + 1'b1;

    end

    always @ (posedge clk_1sec)

    begin

    if (state == Red_st)

    Red <= #1 1'b1;

    else

    Red <= #1 1'b0;

    end

    always @ (posedge clk_1sec)

    begin

    if (state == Green_st)

    Green <= #1 1'b1;

    else

    Green <= #1 1'b0;

    end

    always @ (posedge clk_1sec)

    begin

    if (state == Yel_st)

    Yellow <= #1 time_cnt[0];

    else

    Yellow <= #1 1'b0;

    end

    endmodule

    2008-01-11 13:32:47 補充:

    這是一個簡單紅綠燈的 verilog code, 你自己翻一下 verilog 的書應該不難看懂, 可能要請你自己寫程式驗證, 本人愛寫 verilog code, 但是不喜歡驗證. good luck

    2008-01-14 22:04:08 補充:

    `timescale 1ms/1ns

    module test();

    reg clk_1sec;

    reg reset;

    wire Red, Green, Yellow;

    always @ (clk_1sec)

    clk_1sec <= #500 ~clk_1sec;

    red_green_light red_green_light (.reset (reset), .clk_1sec (clk_1sec), .Red (Red), .Green (Green), .Yellow (Yellow));

    2008-01-14 22:04:46 補充:

    initial begin

    #100;

    $dumpfile ("test.vcd");

    $dumpvars(0,test);

    end

    initial begin

    reset = 1;

    clk_1sec = 0;

    #5100;

    reset = 0;

    #1000000;

    $finish;

    end

    endmodule

    2008-01-14 22:06:37 補充:

    請自己把兩段加在一起唄

    第五行應該有空格, 如下

    input reset; // 1:Reset system

    input clk_1sec; // clock frequency = 1 sec

    output Red, Green, Yellow;

    Source(s): 自己
  • 1 decade ago

    真是的你要別人給你意見就算了...居然還補一句 [或幫我寫一個程式出來]...難怪有老師會說作業如果用知識家僦0分

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