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如何用Verilog HDL設計計算機的程除

最近在設計硬體晶片

使用的硬體描述語言是Verilog HDL

做完加減感覺還算OK

不過乘除就有問題了

像4bit*4bit=8bit...之類進位的問題

就不知道怎麼寫出來

麻煩有知道的大大幫幫忙

1 Answer

Rating
  • 末了
    Lv 4
    1 decade ago
    Favorite Answer

    以下程式 給你參考

    module signed_mult (out, clk, a, b)

    output [7:0] out;

    input clk;

    input signed [3:0] a;

    input signed [3:0] b;

    reg signed [3:0] a_reg;

    reg signed [3:0] b_reg;

    reg signed [7:0] out;

    wire signed [7:0] mult_out;

    assign mult_out = a_reg * b_reg;

    always@(posedge clk)

    begin

    a_reg <= a;

    b_reg <= b;

    out <= mult_out;

    end

    Source(s): 自己
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