請問以下邏輯設計問題 ? ( 原文的 )
1.+Prove the identity of each of the following Boolean equations,using algebraic manipulation:
2.Using DeMorgan's theorem,express the function
(a)with only OR and complement operations
(b)with only AND and complement operations
3.Draw the logic diagram for the following Boolean expressions.The diagram should correspond exactly to the equation.Assume that the complements of the inputs are not available.
4.*find the minterms of the following expressions by first plotting each expression on a map:
5.Optimize the following functions into (1) sum-of-products and (2) product-of-sums forms:
6.Use extraction to find a shared,minimum gate input count,multiple-level implementation for the pair of functions given using AND and OR gates and inverters.
(a)F(A,B,C,D)=Sigma m(0,5,11,14,15),d(A,B,C,D)=Sigma m(10)
(b)G(A,B,C,D)=Sigma m(2,7,10,11,14),d(A,B,C,D)=Sigma m(15)
7.(a)Connect the outputs of three 3-state buffers together,and add additional logic to implement the function
Assume that C,D,and D' are data inputs to the buffers and A and B pass through logic that generates the enable inputs.
(b)Is your design in part(a) free of three-state output conflicts?If not,change the design ig necessary to be free of such conflicts.
請給我中文的過程和解答 , 我知道要翻譯有點困難 , 如果不行的話過幾天我會試著翻譯成中文再 PO 上來 , 謝謝
- Anonymous1 decade agoFavorite Answer
2007-12-19 21:35:05 補充：
2007-12-19 21:43:18 補充：
2007-12-19 21:46:55 補充：
2007-12-19 21:51:43 補充：
004:increase four literals by consensus.
005:decrease four literals by consensus.
I don't have enough time to solve all questions, if you could add the question's time, I will do my best on solving them. I'm too busy to solve them at once.
2007-12-20 21:02:32 補充：
Sorry, when I saw the question again, it is too late. I don't have enough time to solve else quesiotns, several days later, I will add.(if my sentence is wrong, you can modify them.)
2007-12-20 21:05:13 補充：
2007-12-20 21:25:47 補充：
2007-12-20 21:31:07 補充：
- Anonymous6 years ago