我想問八位元加法器的VHDL

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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_unsigned.ALL;

PORT (

A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

cout : OUT STD_LOGIC

);

SIGNAL Y : STD_LOGIC_VECTOR(8 DOWNTO 0);

BEGIN

PROCESS (Y,A,B)

BEGIN

Y (7 DOWNTO 0) <= A+B;

IF A(7) = '1' THEN

IF B(7) = '1' THEN

y(8) <= '1' ;

else

Y(8) <= '0';

END IF;

END IF;

S <= Y(7 DOWNTO 0);

cout <= Y(8);

END PROCESS aa;

END a;

Source(s): myself

library ieee;

use ieee.std_logic_1164.all;

port (x, y : in std_logic;

s, c : out std_logic);

begin

s <= x xor y;

c <= x and y;

end dataflow_3;

library ieee;

use ieee.std_logic_1164.all;

port (x, y, z : in std_logic;

s, c : out std_logic);

port(x, y : in std_logic;

s, c : out std_logic);

end component;

signal hs, hc, tc: std_logic;

begin

port map (x, y, hs, hc);

port map (hs, z, s, tc);

c <= tc or hc;

end struc_dataflow_3;

library ieee;

use ieee.std_logic_1164.all;

port(B, A : in std_logic_vector(7 downto 0);

C0 : in std_logic;

S : out std_logic_vector(7 downto 0);

C8: out std_logic);

port(x, y, z : in std_logic;

s, c : out std_logic);

end component;

signal C: std_logic_vector(8 downto 0);

begin

port map (A(0), B(0), C(0), S(0), C(1));

port map (A(1), B(1), C(1), S(1), C(2));

port map (A(2), B(2), C(2), S(2), C(3));

port map (A(3), B(3), C(3), S(3), C(4));

port map (A(4), B(4), C(4), S(4), C(5));

port map (A(5), B(5), C(5), S(5), C(6));

port map (A(6), B(6), C(6), S(6), C(7));