我想問八位元加法器的VHDL

有誰知道8位元加法器的VHDL怎麼寫嗎

是學校作業~~

會的人就麻煩你幫我解答~~謝謝

2 Answers

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  • 1 decade ago
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    LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    USE IEEE.STD_LOGIC_unsigned.ALL;

    ENTITY adder8bit IS

    PORT (

    A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

    S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

    cout : OUT STD_LOGIC

    );

    END adder8bit;

    ARCHITECTURE a OF adder8bit IS

    SIGNAL Y : STD_LOGIC_VECTOR(8 DOWNTO 0);

    BEGIN

    PROCESS (Y,A,B)

    BEGIN

    Y (7 DOWNTO 0) <= A+B;

    IF A(7) = '1' THEN

    IF B(7) = '1' THEN

    y(8) <= '1' ;

    else

    Y(8) <= '0';

    END IF;

    END IF;

    S <= Y(7 DOWNTO 0);

    cout <= Y(8);

    END PROCESS aa;

    END a;

    Source(s): myself
  • 1 decade ago

    -- 8-bit Adder: Hierarchical Dataflow/Structural

    library ieee;

    use ieee.std_logic_1164.all;

    entity half_adder is

    port (x, y : in std_logic;

    s, c : out std_logic);

    end half_adder;

    architecture dataflow_3 of half_adder is

    begin

    s <= x xor y;

    c <= x and y;

    end dataflow_3;

    library ieee;

    use ieee.std_logic_1164.all;

    entity full_adder is

    port (x, y, z : in std_logic;

    s, c : out std_logic);

    end full_adder;

    architecture struc_dataflow_3 of full_adder is

    component half_adder

    port(x, y : in std_logic;

    s, c : out std_logic);

    end component;

    signal hs, hc, tc: std_logic;

    begin

    HA1: half_adder

    port map (x, y, hs, hc);

    HA2: half_adder

    port map (hs, z, s, tc);

    c <= tc or hc;

    end struc_dataflow_3;

    library ieee;

    use ieee.std_logic_1164.all;

    entity adder_8 is

    port(B, A : in std_logic_vector(7 downto 0);

    C0 : in std_logic;

    S : out std_logic_vector(7 downto 0);

    C8: out std_logic);

    end adder_8;

    architecture structural_8 of adder_8 is

    component full_adder

    port(x, y, z : in std_logic;

    s, c : out std_logic);

    end component;

    signal C: std_logic_vector(8 downto 0);

    begin

    Bit0: full_adder

    port map (A(0), B(0), C(0), S(0), C(1));

    Bit1: full_adder

    port map (A(1), B(1), C(1), S(1), C(2));

    Bit2: full_adder

    port map (A(2), B(2), C(2), S(2), C(3));

    Bit3: full_adder

    port map (A(3), B(3), C(3), S(3), C(4));

    Bit4: full_adder

    port map (A(4), B(4), C(4), S(4), C(5));

    Bit5: full_adder

    port map (A(5), B(5), C(5), S(5), C(6));

    Bit6: full_adder

    port map (A(6), B(6), C(6), S(6), C(7));

    Bit7: full_adder

    port map (A(7), B(7), C(7), S(7), C(8));

    C(0) <= C0;

    C8 <= C(8);

    end structural_8;

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