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請問vhdl 8個輸入2的補數如何寫他的程式

vhdl 8個輸入和8個輸出2的補數如何寫他的程式碼

2 Answers

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  • Ryan
    Lv 4
    1 decade ago
    Favorite Answer

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_unsigned.all;

    use ieee.std_logic_arith.all;

    entity twocom is

    port (

    AI:in std_logic_vector(7 downto 0);

    AO:out std_logic_vector(7 downto 0)

    );

    end twocom ;

    architecture kk of twocom is

    signal Q:std_logic_vector(7 downto 0);

    begin

    process(AI)

    begin

    Q<=not AI;

    AO<=Q+1;

    end process;

    end kk;

    已用max+plusII模擬過了

    2006-02-24 11:08:11 補充:

    小穆似乎對模擬功能需要加強,我輸入00000001,輸出是11111111沒錯,不知道你是如何做simulation的.

    Source(s): myself
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  • 1 decade ago

    那可以請問若是vhdl 8個輸入和8個輸出在加一個輸入s(有號數),2的補數如何寫他的程式碼我是用modelsim模擬的

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