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VHDL~~有錯~~請大大解釋.....3q 20點

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity test_error is

port

(CLK_10M : in STD_LOGIC;

LED : out STD_LOGIC_VECTOR(11 downto 0);

);

end test_error;

architecture A of test_ is

signal Q : STD_LOGIC_VECTOR(23 downto 0);

signal CP : STD_LOGIC ;

signal CNT : STD_LOGIC_VECTOR(3 downto 0);

begin

process (CLK_10M)

begin

if CLK'event and CLK='1' then

Q <= Q+1;

end if;

end process;

CP <= Q(18);

process (CP)

begin

if CP'event AND CP='1' then

if CNT <= '1001' THEN

CNT <= CNT + 1;

ELSE

CNT <= "0010" ;

end if;

end if;

end process;

--State decoder to generate LED outputs

process (CNT)

begin

WITH CNT SELECT

LED <="000000000001" WHEN "0000",

"000000000010" WHEN "0001",

"000000000100" WHEN "0010",

"000000001000" WHEN "0011",

"000000010000" WHEN "0100",

"000000100000" WHEN "0101",

"000001000000" WHEN "0110",

"000010000000" WHEN "0111",

"000100000000" WHEN "1000",

"001000000000" WHEN "1001",

"010000000000" WHEN "1010",

"100000000000" WHEN "1011",

"zzzzzzzzzzzz" WHEN OTHERS ;

end Process;

end A;

1 Answer

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  • 2 decades ago
    Favorite Answer

    library IEEE;

    use IEEE.std_logic_1164.all;

    use IEEE.std_logic_arith.all;

    use IEEE.std_logic_unsigned.all;

    entity test_error is

    port

    (CLK_10M : in STD_LOGIC;

    LED : out STD_LOGIC_VECTOR(11 downto 0); ==>(多了分號)

    );

    end test_error;

    architecture A of test_ is ====>(名稱要一致.要使用test_error)

    signal Q : STD_LOGIC_VECTOR(23 downto 0);

    signal CP : STD_LOGIC ;

    signal CNT : STD_LOGIC_VECTOR(3 downto 0);

    begin

    process (CLK_10M)

    begin

    if CLK'event and CLK='1' then ====>(名稱要一致CLK要改為CLK_10M)

    Q <= Q+1;

    end if;

    end process;

    CP <= Q(18);

    process (CP)

    begin

    if CP'event AND CP='1' then

    if CNT <= '1001' THEN =======>(應該為"1001")

    CNT <= CNT + 1;

    ELSE

    CNT <= "0010" ;

    end if;

    end if;

    end process;

    --State decoder to generate LED outputs

    process (CNT)=========>(這裡不可使用PROCESS,因為with...select事屬於並序

    模式,而process是屬於循序模式.)

    begin

    WITH CNT SELECT

    LED <="000000000001" WHEN "0000",

    "000000000010" WHEN "0001",

    "000000000100" WHEN "0010",

    "000000001000" WHEN "0011",

    "000000010000" WHEN "0100",

    "000000100000" WHEN "0101",

    "000001000000" WHEN "0110",

    "000010000000" WHEN "0111",

    "000100000000" WHEN "1000",

    "001000000000" WHEN "1001",

    "010000000000" WHEN "1010",

    "100000000000" WHEN "1011",

    "zzzzzzzzzzzz" WHEN OTHERS ;=====>(使用"zzzzzzzzzzzz"沒有意義,應該為二進位的字元)

    end Process;

    end A;

    (正確程式如下)

    library IEEE;

    use IEEE.std_logic_1164.all;

    use IEEE.std_logic_arith.all;

    use IEEE.std_logic_unsigned.all;

    entity test_error is

    port

    ( CLK_10M : in STD_LOGIC;

    LED : out STD_LOGIC_VECTOR(11 downto 0)

    );

    end test_error;

    architecture A of test_error is

    signal Q : STD_LOGIC_VECTOR(23 downto 0);

    signal CP : STD_LOGIC ;

    signal CNT : STD_LOGIC_VECTOR(3 downto 0);

    begin

    process (CLK_10M)

    begin

    if CLK_10M'event and CLK_10M='1' then

    Q <= Q+1;

    end if;

    end process;

    CP <= Q(18);

    process (CP)

    begin

    if CP'event AND CP='1' then

    if CNT <= "1001" THEN

    CNT <= CNT + 1;

    ELSE

    CNT <= "0010" ;

    end if;

    end if;

    end process;

    --State decoder to generate LED outputs

    WITH CNT SELECT

    LED <="000000000001" WHEN "0000",

    "000000000010" WHEN "0001",

    "000000000100" WHEN "0010",

    "000000001000" WHEN "0011",

    "000000010000" WHEN "0100",

    "000000100000" WHEN "0101",

    "000001000000" WHEN "0110",

    "000010000000" WHEN "0111",

    "000100000000" WHEN "1000",

    "001000000000" WHEN "1001",

    "010000000000" WHEN "1010",

    "100000000000" WHEN "1011",

    "000000000000" WHEN OTHERS ;

    end A;

    如果還有問題可mail給我...一起討論

    bapomkimo@yahoo.com.tw

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